Method of manufacturing a non-volatile memory cell

ABSTRACT

The present invention relates to a method of manufacturing a non-volatile memory cell. The method comprises forming an ONO stack structure and a mask formed on the ONO stack structure, providing a first etching process to form a first spacer surrounding the mask, removing the first spacer and the ONO stack structure without the first spacer and the ONO stack structure protection, forming an electrical connection layer between the masks, forming a second spacer surrounding the mask, removing the second spacer to form a gate and removing the mask and the ONO stack structure which is under the mask.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a non-volatile memory cell, and more particularly, to a method of manufacturing the non-volatile memory cell has an oxide-nitride-oxide stack structure.

2. Description of the Prior Art

The flash memory mainly comprises a floating gate for storing electric charges, and a control gate disposed on the floating gate for controlling access of data, where the control gate is separated from the floating gate via a dielectric layer formed by an oxide-nitride-oxide (ONO) structure. Therefore, the memory can utilize a principle of thermal electrons or tunneling to store induced electric charges within the overlapped gates so as to store a signal ‘0’ in the memory. If data stored in the memory needs be changed, the only process is to supply a small extra amount of energy to remove electrons stored in the floating gate so as to rewrite data.

The Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is the most common structure of the non-volatile memory cell recently. The nitride silicon layer is a charge trapping medium of SONOS. Its floating gate is made by punching effect or source side injection to save electron in the floating gate as the data. The shortcoming of SONOS is the electron will punch the floating gate when the tunnel between the source and drain is too short. That becomes a problem when SONOS utilizes in smaller memory size. The other shortcoming of SONOS is bad erasing effect that makes date disorder. That is why localized oxide-nitride-oxide memory is produced.

The localized oxide-nitride-oxide memory has good erasing effect because of the localized oxide-nitride-oxide stack structure and the asymmetric structure. The prior localized oxide-nitride-oxide memory manufacture process has at least two photo masks. The first one is formed the localized oxide-nitride-oxide memory and the other one is formed the gate. But, the photo mask pattern becomes dense and the cost and the process increase. Because alignment accuracy is low and failure rate is high, the rework cost increases. The oxide-nitride-oxide stack structure is always inconsistent and the performance of the memory is not good enough.

Therefore, to develop a method of manufacturing the localized oxide-nitride-oxide memory solves the above problem is importance.

SUMMARY OF INVENTION

The present invention provides a method of manufacturing the non-volatile memory cell to solve above problem.

The embodiment according to the present invention provides a method of manufacturing a non-volatile memory cell comprises providing a semiconductor substrate, forming an oxide-nitride-oxide stack structure in the semiconductor substrate, forming a plurality of mask in the oxide-nitride-oxide stack structure, forming a first spacer around the mask, removing the oxide-nitride-oxide stack structure without the first spacer cover and the mask cover, removing the first spacer, forming an electrical conduction layer between the masks and the height of the electrical conduction layer is lower than the height of the mask, forming a plurality of a second spacer around the mask in the electrical conduction layer, removing the electrical conduction layer without the second spacer cover, and removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover.

The other embodiment according to the present invention provides a method of manufacturing a non-volatile memory cell comprises providing a semiconductor substrate, forming a trapping layer in the semiconductor substrate, forming a plurality of mask in the trapping layer, forming a first spacer around the mask, removing the trapping layer without the first spacer cover and the mask cover, removing the first spacer, forming an electrical conduction layer between the masks and the height of the electrical conduction layer is lower than the height of the mask, forming a plurality of a second spacer around the mask in the electrical conduction layer, removing the electrical conduction layer without the second spacer cover; and removing the second spacer, the mask and the trapping layer with the mask cover.

The present invention uses spacers as self-alignment masks to form the oxide-nitride-oxide stack structure and the gate. Therefore, the present invention has no redundant masks as the prior art, decreases the rework rate. The oxide-nitride-oxide stack structure according to the present invention is consistent and memory performs stably.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 to 11 are the flowcharts of the method of manufacturing the non-violent memory cell according to the present invention.

DETAILED DESCRIPTION

Please refer to FIGS. 1 to 11. FIGS. 1 to 11 are the flowcharts of the method of manufacturing the non-violent memory cell according to the present invention. Please refer to FIG. 1, the semiconductor chip 10 is provided the thermal oxidation, chemical vapor deposition and priming process to form the oxide-nitride-oxide stack structure 14, the mask layer 18 and the resist layer (not shown) individually. The photolithography process is provided and the resist layer is exposed by a mask pattern (not shown) to form the resist mask 19. The mask layer 18 without the resist mask 19 cover is removing by the etching process to form the mask 22. Furthermore, the ways to form the mask 22 are not only the photolithography and etching process, but also forming the mask 22 by the photo-chemical low-k material directly.

Please refer to FIG. 2. After removing the resist mask 19, the surface of the oxide-nitride-oxide stack structure 14 is formed the spacer 34 surrounded the mask 22 by depositing the spacer layer 24 and etching the spacer layer 24 back. Then, the spacer 34 is a self-aligned mask for the etching process to remove the oxide-nitride-oxide stack structure 14 without the mask 22 cover and the spacer 34 cover. And, the mask 22 and the spacer 34 surrounded the mask 22 are formed like FIG. 3.

Especially, the buffer nitride layer 16 is etching stop layer to protect the completeness of the oxide-nitride-oxide stack structure 14, when the mask layer 18 is etched. The lowest oxide silicon layer 36 of the oxide-nitride-oxide stack structure 14 is etching stop layer for avoiding the surface of the semiconductor chip 10 polluting, when the spacer 34 is the self-aligned mask, and the buffer nitride layer 16 and the partial oxide-nitride-oxide stack structure 14 are etched. Otherwise, the materials of the buffer nitride layer 16, the mask layer 18 and the spacer layer 24 are changed according to the condition of the process, the product design and the uniform of the etching process. The materials are considered for the etching ratio.

Please refer to FIG. 4. The spacer 34 and the buffer nitride layer 16 with the spacer 34 cover are removed. The gate oxide layer 42 between etch the oxide-nitride-oxide stack structure 14 is formed by the thermal oxidation process. Before forming the gate oxide layer 42, the oxide-nitride-oxide stack structure 14 could be removed completely.

Please refer to FIG. 5. The electrical conduction layer 52 is deposited on the semiconductor chip 10 uniformly. The material of the electrical conduction layer 52 could be any of the polycrystalline silicon layer, the silicide layer and the polycrystalline silicon layer and the silicide layer combined layer. Then, the electrical conduction layer 52 is the stop layer for the chemical mechanical polishing (CMP) until the electrical conduction layer 52 and the mask 22 have the same height like FIG. 6. The electrical conduction layer 52 is etched by the etching back process until the electrical conduction layer 52 is lower than the mask 22 like FIG. 7.

The semiconductor chip 10 is deposited the spacer layer 84 like FIG. 8. The spacer layer 84 is etched until the surface of the semiconductor chip 10 by the etching back process and formed the spacer 94 surrounded the mask 22 like FIG. 9. The spacer 94 is the gate mask for the gate self-aligned etching process and the etching process is etched the electrical conduction layer 52 to form the gate 102 like FIG. 10. Providing the doping process drives ion into the side of the gate 102 without connecting with the mask 22 to from the drain (not shown). And, the spacer 94 is removed by the etching process.

After removing the mask 22, the buffer nitride layer 16 and the oxide-nitride-oxide stack structure 14 with the mask 22 cover, the source domain 112 is formed in the original position of the mask 22. Then, the source domain 112 is doped by ion to form the source 114. The dielectric layer (not shown) is formed on the semiconductor chip 10. The contact window (not shown) is formed on the individual drain (not shown) by the photolithography and etching process. The contact window is filled with the metal to form the metal contact and the multilevel interconnection, and the passivation layer is formed finally. The non-violent memory cell is made completely.

Compare to the prior art, the oxide-nitride-oxide memory according to the prior art has at least two photo masks. The first one is formed the localized oxide-nitride-oxide memory and the other one is formed the gate. But, the photo mask pattern becomes dense and the cost and the process increase. Because the alignment accuracy is low and the failure rate is high, the rework cost increases. The oxide-nitride-oxide stack structure according to the prior art is always inconsistent and the performance of the memory is not good enough. But the present invention uses spacers 34, 39 as the self-aligned mask to form the oxide-nitride-oxide stack structure 14 and the gate 102 individually. Therefore, the present inventions has no redundant mask as the prior art, decreases the rework rate, the oxide-nitride-oxide stack structure is consistent and memory performances stably.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. 

1. A method of manufacturing a non-volatile memory cell comprising: providing a semiconductor substrate; forming an oxide-nitride-oxide stack structure in the semiconductor substrate; forming a plurality of mask in the oxide-nitride-oxide stack structure; forming a first spacer around the mask; removing the oxide-nitride-oxide stack structure without the first spacer cover and the mask cover; removing the first spacer; forming an electrical conduction layer between the masks and the height of the electrical conduction layer is lower than the height of the mask; forming a plurality of a second spacer around the mask in the electrical conduction layer; removing the electrical conduction layer without the second spacer cover; and removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover.
 2. The method of claim 1, wherein the mask is made by depositing a mask layer above the oxide-nitride-oxide stack structure and a photolithography process.
 3. The method of claim 1, wherein the first spacer is made by depositing a first spacer layer above the mask and an etching back process to etch the first spacer layer until the surface of the oxide-nitride-oxide stack structure.
 4. The method of claim 1, wherein the oxide-nitride-oxide stack structure comprises a buffer nitride layer above the oxide-nitride-oxide stack structure and the plurality of the mask is formed in the surface of the buffer nitride layer.
 5. The method of claim 4, wherein the process of removing the first spacer and the oxide-nitride-oxide stack structure with the mask cover is removed the buffer nitride layer without the first spacer cover and the mask cover simultaneously.
 6. The method of claim 1, wherein the method further comprises forming a gate oxide layer between each the oxide-nitride-oxide stack structure in the semiconductor substrate after the first spacer is removed.
 7. The method of claim 1, wherein the electrical conduction layer is made by an electrical conduction layer deposition, a chemical mechanical polishing and an electrical conduction layer etching back process.
 8. The method of claim 1, wherein the second spacer is made by depositing a second spacer layer above the mask and a etching back process to etch until the surface of the electrical conduction layer.
 9. The method of claim 8, wherein the second spacer is a self-alignment gate mask to definite the gate of the non-volatile memory cell.
 10. The method of claim 1, wherein the method further comprising forming a drain of the non-volatile memory cell after removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover.
 11. The method of claim 1, wherein the method further comprising forming a source of the non-volatile memory cell after removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover.
 12. A method of manufacturing a non-volatile memory cell comprising: providing a semiconductor substrate; forming a trapping layer in the semiconductor substrate; forming a plurality of mask in the trapping layer; forming a first spacer around the mask; removing the trapping layer without the first spacer cover and the mask cover; removing the first spacer; forming an electrical conduction layer between the masks and the height of the electrical conduction layer is lower than the height of the mask; forming a plurality of a second spacer around the mask in the electrical conduction layer; removing the electrical conduction layer without the second spacer cover; and removing the second spacer, the mask and the trapping layer with the mask cover.
 13. The method of claim 12, wherein the trapping layer is made form a oxide-nitride-oxide stack structure.
 14. The method of claim 13, wherein the mask is made by depositing a mask layer above the oxide-nitride-oxide stack structure and a photolithography process.
 15. The method of claim 13, wherein the first spacer is made by depositing a first spacer layer above the mask and an etching back process to etch the first spacer layer until the surface of the oxide-nitride-oxide stack structure.
 16. The method of claim 1 3, wherein the oxide-nitride-oxide stack structure comprises a buffer nitride layer above the oxide-nitride-oxide stack structure and the plurality of the mask is formed in the surface of the buffer nitride layer.
 17. The method of claim 16, wherein the process of removing the first spacer and the oxide-nitride-oxide stack structure with the mask cover is removed the buffer nitride layer without the first spacer cover and the mask cover simultaneously.
 18. The method of claim 13, wherein the method further comprises forming a gate oxide layer between each the oxide-nitride-oxide stack structure in the semiconductor substrate after the first spacer is removed.
 19. The method of claim 13, wherein the electrical conduction layer is made by an electrical conduction layer deposition, a chemical mechanical polishing and an electrical conduction layer etching back process.
 20. The method of claim 13, wherein the second spacer is made by depositing a second spacer layer above the mask and a etching back process to etch until the surface of the electrical conduction layer.
 21. The method of claim 20, wherein the second spacer is a self-alignment gate mask to definite the gate of the non-volatile memory cell.
 22. The method of claim 13, wherein the method further comprising forming a drain of the non-volatile memory cell after removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover.
 23. The method of claim 13, wherein the method further comprising forming a source of the non-volatile memory cell after removing the second spacer, the mask and the oxide-nitride-oxide stack structure with the mask cover. 